1. Field of the Invention
This invention relates to improving processor performance, and more particularly to a method and apparatus for predicting silent stores and bypassing prior issued store instructions with unexecuted load instructions.
2. Background Information
Out-of-order processors need to obey data dependancies. Register dependancies are easily identified by register names. Memory dependancies, however, are difficult to identify since the addresses of load and store instructions are only known at the time of execution. A load instruction typically transfers data from memory to a general register, a floating-point register, or a pair of floating-point registers. Store instructions typically transfer data from a general or floating-point register to memory. Processors, such as the P6 family, assume that load instructions depend on all previous store instructions issued, but not yet executed. Therefore, no load instructions can be advanced ahead of a previous issued store address operation. This restricts the scheduler by introducing false dependencies which, results in loss of performance.
Memory disambiguation is the ability to resolve whether a load address and a store address refer to the same address, i.e. the addresses would collide, or whether the addresses are different. This prediction would allow the advancing of load instructions before a store instruction if it is predicted not to collide.
Some of the previous approaches include the following. A scheme to never advance load instructions before a previous issued store instruction. Also, there are various types of hardware memory, software assisted memory, and architecture assisted memory disambiguation schemes. Also, several approaches to memory disambiguation have been introduced to try to predict when an address of a load instruction and an address of a previously issued store instruction will differ.